Technology CAD is the craft of simulating a semiconductor before it exists: the fabrication steps in a process simulator, the resulting device in a device simulator, and the handoff to the compact models circuit designers consume. Synopsys describes the TCAD suite as tools that simulate the fabrication, operation, and reliability of semiconductor devices, using physical models for the wafer fabrication steps and device operation . The people in this discipline sit between process integration and circuit design, and their output is a prediction somebody spends mask sets to test. That position, mid-chain and heavily quantified, is why the seats are hard to fill: the craft needs physics, numerics, and an industrial calibration discipline in one person.
Challenges in Technology CAD Recruiting
TCAD simulation sits between the process recipe and the device that results
The core of the craft is a coupled chain: a process simulator steps through implant, diffusion, oxidation, and annealing with models calibrated against equipment vendor data, then hands the resulting structure to a device simulator for electrical, thermal, and optical characteristics . The process side carries models for transient-enhanced diffusion, {311} defects, interstitial clusters, and kinetic Monte Carlo atomistics, because a junction is not a curve on a slide, it is the residue of every anneal that came before . The chain is only as good as its weakest calibration, since a process model tuned on one anneal condition quietly lies about the next. Process engineers speak recipes; device engineers speak current-voltage curves. The TCAD engineer is the person who can walk a process change through both, and that middle position is exactly what makes the role visible in an organization chart but hard to find on a job board.
Process emulation trades accuracy for turnaround inside DTCO loops
Full physical process simulation is expensive, so the industry built a faster lane. Sentaurus Process Explorer is a fast 3D process emulator that produces realistic structures from GDSII mask data and a process recipe, feeding resistance-capacitance extraction in design technology co-optimization loops where deposition complexity meets limited budget . Process emulation engineers work at the boundary between fabrication and layout: they know which physics can be approximated, where the emulated structure diverges from the simulated one, and how much of that error lands in the extracted parasitics. It is a different discipline from deep physical simulation, with different tools, different turnaround targets, and different instincts about approximation.
Physics based semiconductor modeling splits drift-diffusion from Monte Carlo transport
Device simulation is a solver hierarchy, and engineers specialize by which rung they work. Drift-diffusion solves the semiconductor equations cheaply and covers most silicon work; hydrodynamic models add carrier energy; and very small transistors demand the Boltzmann transport equation solved by spherical harmonic expansion or Monte Carlo methods . Sentaurus Device supports the full ladder, plus quantization via Schrödinger solutions and tunneling models for heterostructures, power devices, and memory . The hiring question is which rung a candidate actually owns. Someone who has converged drift-diffusion on a power IGBT and someone who has run Monte Carlo on a nanosheet both call themselves device simulation engineers, and the two skill sets share a mesh file and little else.
Quantum transport simulation begins where the drift-diffusion approximation ends
At a few nanometers, semiclassical transport stops describing the channel. Quantum transport simulation uses the non-equilibrium Green's function method, typically coupled to density functional or semi-empirical Hamiltonians, to compute transmission, current-voltage curves, subthreshold slope, and drain-induced barrier lowering for nanoscale devices . The vocabulary is different from the rest of TCAD: self-energies, electrode extensions, and transmission spectra instead of carrier concentrations and mobility. The population is mostly PhD-level and mostly outside industrial fabs, which makes hiring for production quantum transport work a two-step problem: find someone who can run the physics, then teach them the industrial part that physics programs skip.
Compact modeling converts physics into a circuit simulator's equations
Compact modeling is where device physics becomes mathematics a circuit designer can run. The BSIM family defines the standard models: BSIM-CMG for common multi-gate FinFETs, BSIM-IMG for independent-gate devices, BSIM-SOI, BSIM-BULK, and the legacy BSIM4 . BSIM-CMG was selected as the first industry-standard compact model for FinFETs, which is why every advanced-node PDK converges on it . The compact modeler's daily work is continuity, symmetry tests, higher-order derivatives, and parameters that survive a Monte Carlo corner. The discipline is a narrow one: the number of people who have built or globally extracted an industry-standard compact model against real silicon is small, and most of them are not looking. Foundries guard these engineers, because the model is the node's contract with every design team that will ever use it.
Device parameter extraction is the bridge TCAD hands to SPICE
Between the technology and the design kit sits device parameter extraction. The extractor takes TCAD simulation data or measured silicon curves and fits the compact model's parameters so that SPICE reproduces the device, with research now applying machine learning to the fit . Extraction work is the classic hidden step: a CV that says TCAD simulation does not say whether the candidate ran the simulation, built the extraction flow, or defended the fitted model in front of a modeling review. The extractor owns the error budget. A sub-half-percent RMS error on the gate capacitance curve is achievable with modern extraction; a wrong corner at high drain bias is still a fail, and telling the difference is the job .
Finite element device modeling claims collapse without the mesh they converged
The probes for this craft are numerical as much as physical. Finite element device modeling lives or dies on discretization: which mesh, which refinement regions, what the convergence looked like at breakdown voltage, and what the residual did when the solver refused. A mesh that resolves the channel but smears the drain junction produces beautiful curves for the wrong device, and only the person who built the deck knows which one it was. Ask a candidate which solver they ran for which device, how the IV curves compared to silicon, and what the last divergence taught them . Ask how they calibrated a model against data and which parameter they refused to touch. The owners answer in calibration targets and turnaround times; the witnesses answer in tool names.
The cost of a miss is paid in silicon. A simulation that does not match the measured device sends process development down a wrong branch for a full node cycle, and a compact model that fits the curves but mispredicts the device surfaces only after circuit designers have built on it. The discipline is small enough that the right candidate is usually found by asking which mesh they converged and which extraction they defended, not by scanning for TCAD.
References
- Sentaurus TCAD: Industry-Standard Process and Device Simulators — Synopsys. (accessed 2026-09-28)
- Sentaurus Process: An Advanced 1D, 2D and 3D Process Simulator — Synopsys. (accessed 2026-09-28)
- Sentaurus Device: An Advanced Multidimensional (1D/2D/3D) Device Simulator — Synopsys. (accessed 2026-09-28)
- QuantumATK Simulation Engines for Advanced Semiconductor Development — Synopsys. (accessed 2026-09-28)
- The BSIM Family — BSIM Group, UC Berkeley. (accessed 2026-09-28)
- BSIM - SPICE Models Enable FinFET and UTB IC Designs — IEEE Access. (accessed 2026-09-28)
- iPREFER: An Intelligent Parameter Extractor based on Features for BSIM-CMG Models — arXiv (DAC 2024). (accessed 2026-09-28)