Semiconductor etching is the subtractive half of patterning: the plasma etching, reactive ion etching (RIE) and wet processes that transfer a resist image into dielectrics, conductors and silicon, and the profile control that decides whether a device works at all. Its engineers sit at chamber makers and fabs, and the discipline splits along film chemistry and aspect ratio rather than job title. Lam Research, whose core franchise spans deposition and etch, posted $20.6 billion in calendar 2025 revenue with $2.3 billion in R&D . Tokyo Electron counts plasma etch and gas chemical etch among its four key process families .
Challenges in Semiconductor Etch Recruiting
Plasma etching climbs aspect ratios the chamber design never anticipated
Plasma etching is defined by the holes and trenches it must dig. 3D NAND now demands channel holes through stacks of hundreds of layers, at aspect ratios that strain every element of the chamber. Tokyo Electron's integrated report describes strengthening cryogenic etch for deep holes and trenches in NAND, and its Q3 FY2025 disclosures record a high-volume process-of-record win in channel hole etching . The engineering spans RF power delivery, gas chemistry, ion energy control and wafer temperature, and at high aspect ratio those knobs all interact: cooling the wafer changes polymer deposition, which changes the taper, which changes the next layer's landing. The people who own high-aspect-ratio etch are among the most concentrated populations in the industry. Memory makers and their two main chamber suppliers employ nearly all of them, and each has more open etch seats than it can fill. The demand signal is direct: every additional NAND layer and every new DRAM architecture increases the number of high-aspect-ratio etches per wafer, while the pool of engineers who have held one of those processes in volume grows only through internal promotion.
Reactive ion etching (RIE) work fragments across dielectric, conductor and memory stacks
Reactive ion etching (RIE) is one name for three trades. Dielectric etch opens contacts and vias with fluorocarbon chemistry and endpoint on underlying films. Conductor etch sculpts gates and interconnects with chlorine-based chemistry, then worries about profile and damage. Memory etch digs stacks: channel holes, slits and staircases. Lam built its Sense.i platform across dielectric, conductor and 3D NAND etch applications, and that breadth is the exception rather than the rule . Most practitioners spend a decade inside one trade, because the chemistry families, endpoint techniques and defect signatures do not carry over. A screening process that reads RIE and stops there will shortlist a conductor specialist for a dielectric seat and discover the gap three interviews in.
Deep reactive ion etching (DRIE) anchors the MEMS and TSV niches
Deep reactive ion etching (DRIE) is the Bosch-process corner of the discipline, where alternating etch and passivation cycles cut near-vertical walls tens of microns deep into silicon. Its practitioners build MEMS, through-silicon vias and microfluidic structures rather than transistors. KLA's specialty semiconductor segment, which sells etch and plasma dicing tools, marks how this corner sits apart from the front-end mainstream . The population is small, scattered across device makers, research institutes and packaging lines, and it carries its own vocabulary: scallop control, notching, release protection. A DRIE engineer and a front-end RIE engineer share a plasma source and almost no process knobs, yet both list plasma etching on their CVs. The two are hired against entirely different briefs.
Atomic layer etching (ALE) arrives wherever selective etching becomes mandatory
Atomic layer etching (ALE) runs the etch analog of ALD: self-limited surface chemistry removes one atomic layer at a time, which is what gate-all-around transistors need when they trim nanosheets and strip sacrificial silicon germanium without touching the channel. Selective etching is the growth frontier of the discipline. Tokyo Electron's Certas line does plasma-less gas chemical etch precisely because high-selectivity steps increasingly demand chemistry without ion bombardment . ALE engineers combine surface chemistry with plasma pulsing, and most of them sit inside chamber OEMs and leading-edge fabs, because the technique has not spread to the mature-node world. Hiring for ALE usually means hiring ahead of published process flows: the work exists inside programs whose details never appear in job postings, which makes the search a matter of knowing which organizations are running which experiments.
Wet etching survives in cleans, releases and specialty substrates
Wet etching never left the fab; it receded to where liquid chemistry is still the best tool. Sacrificial layer release in MEMS, specialty substrate thinning, and the cleans that bookend dry steps all live in baths and sprays, governed by etch rates, selectivity ratios and temperature rather than plasma. The population skews senior, and its knowledge is documented even more thinly than plasma work: a wet etch engineer's selectivity tables often exist only in the engineer's head. Because the discipline looks unglamorous from outside, employers rarely compete for these people until a release process fails, at which point the search starts with almost no pipeline to draw on. The best wet etch hires have often spent years outside the front-end entirely, in compound semiconductor fabs, MEMS lines and substrate houses, where liquid chemistry still carries the process.
Etch process development ties chamber design to sidewall profile control
Etch process development is profile engineering. Hitachi's R&D group describes the defects that define the trade: high-aspect-ratio holes that etch tilted, bowed or twisted, defects that metrology must then measure in three dimensions . Imec's forksheet work shows the same trade at the transistor: silicon germanium etched away to release nanosheet channels, source/drain etched back before epitaxial regrowth . Imec's CFET program added an in-situ capping step to protect the gate during source/drain recess etch, a fix that exists only because the etch engineers kept losing the hardmask . Each of those is etch process development in its pure form: a sequence where chamber hardware, gas chemistry and timing decide a profile that metrology judges later. The engineers who own such steps quote taper, bow, selectivity and microloading. The ones who only witnessed them quote tool names.
Stack etch ownership separates dry etching veterans from recipe tourists
Every dry etching CV lists plasma, RIE, chemistries, chambers. The separation is in what the candidate can reconstruct about the stacks they actually etched. Which stack, how many layers, and which film were you actually opening? What was the selectivity budget between mask and film, and what did you change when it broke? What did the sidewall profile look like after etch, and which knob moved it? Tokyo Electron's process-of-record win in NAND channel hole etching is the reference standard: owning such a win means surviving a customer's yield ramp, not running a demo . The cost of a miss is a profile that will not print. An etch seat filled below its spec breaks a taper and bow budget across the entire flow, and every correction cycle burns the senior process time the ramp was supposed to conserve.
References
- Lam Research Company Overview — Lam Research. (accessed 2026-09-28)
- Tokyo Electron Integrated Report 2025 — Tokyo Electron. (accessed 2026-09-28)
- Tokyo Electron Q3 FY2025 Financial Announcement — Tokyo Electron. (accessed 2026-09-28)
- Deep Learning Model for 3D Profiling of HAR Features Using High-Voltage CD-SEM — Hitachi Research and Development. (accessed 2026-09-28)
- Outer Wall Forksheet: Bridging Nanosheet and CFET Device Architectures — imec. (accessed 2026-09-28)
- Imec Shows Working CFET Devices for Next-Gen 0.7nm Chip Designs — eeNews Europe. (accessed 2026-09-28)
- KLA Corporation Form 10-K, Fiscal 2025 — KLA Corporation. (accessed 2026-09-28)