Photonics in this craft is the engineering of light on a chip: photonic integrated circuits (PICs) that generate, route, modulate, and detect it in silicon photonics, indium phosphide, and silicon nitride, plus the optoelectronics that wrap those dies. Demand sits on foundry-compatible integrated photonics for optical communications. Mordor Intelligence puts the silicon photonics market at USD 2.83 billion in 2025 and USD 3.96 billion in 2026, on a path to USD 13.18 billion by 2031 . IEEE Spectrum reports typical data-center transceivers still at 100 Gb/s per lane, ramping toward 200 Gb/s, with 400 Gb/s per lane as the next milestone; Imec has shown a silicon-germanium electro-absorption modulator at 448 Gb/s on 300 mm wafers . Companies hire people who have taped out to a named process design kit, attached a III-V laser, and packaged fiber to a PIC.
Challenges in Photonics Recruiting
Silicon photonics foundries lock PIC tape-outs to a PDK
A photonic integrated circuit is only as transferable as the process it was drawn against. AIM Photonics fabricates silicon photonics multi-project wafers at the Albany NanoTech Complex on 300 mm tools, with separate active, passive, silicon-nitride, low-loss, and quantum-flex stacks, and it points InP shuttle work to Sandia rather than mixing the two materials on the same line . Imec’s iSiPP200 platform ships a silicon-validated PDK on 200 mm, with III-V lasers added by wafer-scale flip-chip or micro-transfer printing; iSiPP300 adds through-silicon vias and microbumps for the next package generation . A designer who closed design-rule checks on GlobalFoundries’ AMF process is not interchangeable with one who used AIM PDK 8.0 or Imec’s MPW subset, even when both list the same circuit simulator. NLM Photonics’ 1.6T and 3.2T silicon-organic hybrid PICs were sampled on GF’s AMF GP process, with a second-generation tape-out on AMF HP and a PDK in development for HP PDK 6.0 . Mordor’s wafer split makes the same point at market scale: 300 mm substrates already held 62.33% of silicon photonics revenue in 2025 . People who have never submitted a mask to one of those lines are still doing photonics. They are not doing this job.
Optical communications still splits InP gain from silicon photonics volume
Silicon does not lase. Optical communications products that need on-chip gain therefore live on indium phosphide, or they bolt III-V dies onto a silicon photonics wafer. IEEE Spectrum is blunt about the trade: InP remains limited by smaller wafers and higher manufacturing cost, which is why groups keep pushing silicon modulators and hybrid organic stacks instead of abandoning the CMOS line . Openlight’s open-market Si-III-V platform puts distributed-feedback lasers and electro-absorption modulators capable of exceeding 224 Gb/s on silicon, aimed at single-chip transmitter PICs for 1.6 Tb/s and 3.2 Tb/s transceivers . IEEE’s Heterogeneous Integration Roadmap records Intel shipping more than 8 million PICs with more than 32 million integrated on-chip lasers and a FIT rate below 0.1, which is volume evidence that laser-on-wafer attach can be a manufacturing discipline, not a laboratory stunt . Europe is still trying to give InP the same horizontal foundry model silicon already has. JePPIX was built to move InP PICs out of a handful of vertically integrated houses and into an open-access, PDK-driven pilot line with a target of taking designs from concept to market in under 24 months . TNO, SMART Photonics, PhotonDelta, and High Tech Campus Eindhoven broke ground in March 2026 on what they describe as the first industrial 6-inch InP photonic-chip foundry, a EUR 150 million PIXEurope project under the European Chips Act, initially staffing about 40 specialists . A coherent InP designer, a silicon-photonics transceiver layout engineer, and a heterogeneous-attach process engineer can share a title and still be unable to cover one another’s mask.
Integrated photonics packaging decides whether a PIC leaves the wafer
Die yield is not product yield. The IEEE roadmap traces transceiver packaging from wire-bonded one-dimensional multi-chip modules to 2.5D flip-chip copper pillars on a silicon-photonics interposer and then to three-dimensional stacks that use through-silicon vias, each step tightening I/O pitch and raising warpage and coupling-loss risk when a fiber-array unit is attached to a large substrate . Co-packaged optics puts the optical engine on the same substrate as the switch ASIC; linear pluggable optics keep a QSFP or OSFP faceplate and throw equalization back onto the host. Those are different thermal and serviceability problems, even when the PIC layout looks familiar. Imec’s 300 mm platform lists TSVs and embedded microbumps as exploratory options, not as a default the datacom designer already owns . AIM Photonics’ Rochester test, assembly, and packaging line exists because Albany can make a wafer that Rochester still has to fiber-attach, bump, and measure . Optica’s NLM note is useful as industry context: silicon photonics already accounts for more than half of the transceiver market, yet the company still had to pair a materials change with a named fab and a design house to get 1.6T and 3.2T dies into sampling . The scarce people have owned fiber-to-chip loss, known-good-die test, and a package that survived temperature and humidity.
Photonic sensors on silicon nitride do not reuse datacom PDKs
Mordor forecasts silicon photonic sensors as the fastest product slice, at a 28.74% compound rate through 2031, which is a different demand curve from transceivers that already hold 47.64% of revenue . The devices look related because both can be a microring on a silicon wafer. They are not the same job. A 2026 Journal of Physics: Photonics review of clinical silicon photonic biosensors puts the hard work on biofunctionalization, antifouling, and microfluidics: silanization chemistry that has to hold in serum or urine, receptors placed into small multiplexed windows, and architectures that run from fully integrated optoelectronic packages to disposable cartridges . Silicon nitride is the usual waveguide because loss can sit below 0.1 dB/cm, the thermo-optic response is weaker than silicon, and the stack is CMOS-compatible; SOI remains available at telecom wavelengths, but the review treats surface chemistry as the translational bottleneck, not modulator bandwidth . AIM’s silicon-nitride-only passive PIC, with a trench that exposes the nitride, exists specifically for sensor and low-fluorescence work rather than for a Ge photodiode transceiver flow . A candidate who has qualified a 400G DR4 PIC has not thereby qualified a label-free multiplexed biosensor. The interview has to ask what fluid touched the chip, how the surface was prepared, and which resonance shift they trusted.
Nonlinear photonics on 300 mm SiN sits outside transceiver foundries
Kerr soliton microcombs are now being written on the same 300 mm silicon-nitride lines used for other integrated photonics, which creates a false sense that a datacom PDK engineer can pick up nonlinear photonics. A 2025 Optics Letters paper from NIST and AIM Photonics reports broadband soliton generation on AIM’s 300 mm wafers using a lower-temperature, lower-stress PECVD nitride about 700 nm thick, with thickness variation of plus or minus 2% across the wafer, aimed at alkali-atom clock lines, LiDAR, and other applications that need a chip-scale frequency comb . Conventional LPCVD nitride combs were already standard up to 200 mm; the paper’s point is that the high-temperature, high-stress LPCVD route fights 300 mm integration with electronics . That is a dispersion, Q-factor, and film-stress problem, not a PAM4 link budget. Nanophotonics inverse-design papers that produce a compact coupler or a free-form scatterer sit even further from a production PDK: the geometry may be beautiful and still be undraggable in a foundry layer stack. Hiring for a comb, a quantum-adjacent SiN circuit, or a visible-band sensor as if it were a 1.6T transmitter wastes the first two MPW cycles.
Optoelectronics titles hide which PIC process a candidate owned
The label optoelectronics is shared by people who have designed a silicon-photonics modulator, grown or bonded a III-V gain block, packaged a receiver optical engine, or published a nanophotonics resonator. CVs collapse that into PIC, Python, and a simulator name. The split that matters is process ownership. One candidate taped out an O-band DR8 on a 300 mm SOI PDK and can discuss heater efficiency and Ge photodiode responsivity. Another owned an InP coherent PIC through a JePPIX-style building-block kit and can discuss on-chip lasers, not grating couplers to an external source . A third ran heterogeneous attach—die-to-wafer micro-transfer printing, flip-chip, or wafer-to-wafer molecular bonding—and lives in contamination rules and bond-interface loss, which is the roadmap’s actual integration taxonomy . A fourth functionalized a SiN ring for a biofluid and never closed a transceiver eye. Screening on the word PIC selects fluency. The work is the mask, the attach, and the package.
Verifying silicon photonics ownership after a PIC tape-out
Assessment failure in this seat is expensive because an MPW cycle and a package revision are slow, and because a wrong platform hire will not show up on a tool-list screen. The conversation has to recover the foundry, the PDK version, the devices the person owned on that reticle, and the metric they will still defend: insertion loss, TDECQ, bit-error rate, fiber-array coupling, ring drift with temperature, or laser FIT if they owned heterogeneous attach . Ask what changed after the first lot—a process corner, a coupler, a bond void, a FAU gap—and who signed the change. A candidate who can only walk through a simulated circuit has not owned a PIC. A miss here does not stay in recruiting. It shows up as a 1.6T engine that cannot be coupled, a sensor cartridge whose surface chemistry will not hold, or a comb program that inherited a datacom PDK and a year of wrong film stress.
References
- Silicon Photonics Market Size, Growth Drivers and Industry Analysis, 2031 — Mordor Intelligence. (accessed 2026-09-27)
- Optical Interconnects: 400 Gb/s Milestone in Reach — IEEE Spectrum. (accessed 2026-09-27)
- NLM Photonics Samples Silicon Organic Hybrid PICs Manufactured at GlobalFoundries — Optica. (accessed 2026-09-27)
- Silicon Photonics Multi-Project Wafer (MPW) — AIM Photonics. (accessed 2026-09-27)
- Silicon photonics foundry services — imec. (accessed 2026-09-27)
- Heterogeneous Integration Roadmap, Chapter 9: Photonics (2025 Rev 0.9) — IEEE Electronics Packaging Society. (accessed 2026-09-27)
- TNO and High Tech Campus Eindhoven begin construction of first 6-inch indium phosphide photonic chip foundry — Semiconductor Today. (accessed 2026-09-27)
- JePPIX Pilot Line in a nutshell — JePPIX. (accessed 2026-09-27)
- Silicon photonic biosensors for clinical diagnostics: system integration and multiplexing strategies — Journal of Physics: Photonics (IOP Publishing). (accessed 2026-09-27)
- 300 mm wafer-scale SiN platform for broadband soliton microcombs compatible with alkali atomic references — Optica Publishing Group (Optics Letters). (accessed 2026-09-27)
- Silicon Photonics Platform with Heterogeneously Integrated Lasers and EAMs for 1.6/3.2T — Optica Publishing Group (OFC 2025). (accessed 2026-09-27)